Technical Field
The present invention relates to a controller for a power converter in which an output unit includes a filtering reactor, the controller having an improved carrier generation scheme for obtaining control signals for semiconductor switching elements of the power converter.
Background Art
FIG. 5 illustrates a power converter in which two uninterruptible power supplies 100A and 100B are connected between a power system 101 and a load 109.
Both uninterruptible power supplies 100A and 100B have the same configuration. Next, the configuration and operation of one of the uninterruptible power supplies 100A will be described.
The uninterruptible power supply 100A converts AC power from the power system 101 to DC power using a rectifier and uses that DC power to charge a battery. The DC power from the battery is then converted back to AC power using an inverter and supplied to a load 109.
The rectifier includes a capacitor 102 and a reactor 103 that form an input filter and a rectifier converter 104 constituted by a power semiconductor switching element. The inverter includes an inverter converter 106 constituted by a power semiconductor switching element and a reactor 107 and a capacitor 108 that form an output filter.
The rectifier converter 104 and the inverter converter 106 are typically single-phase full-bridge circuits or three-phase full-bridge circuits.
FIG. 6 is a block diagram illustrating controllers for the rectifier converter 104 and the inverter converter 106. Note that in the controllers illustrated in FIG. 6, the AC portions are provided for each phase according to the number of phases (single-phase or three-phase) of the rectifier converter 104 and the inverter converter 106 for the power system 101 and the load 109.
First, the configuration and operation of the controller for the rectifier converter 104 will be described.
A voltage detector 202 detects a DC voltage E from a battery 105, and a subtractor 207 calculates the difference between a target DC voltage E* and the detected DC voltage E. A regulator 208 brings the voltage difference to zero, and the output of the regulator 208 is input to a multiplier 209. Furthermore, a voltage detector 201 detects an AC input voltage, and the detected voltage is multiplied with the output of the regulator 208 in the multiplier 209 in order to obtain an input current command.
Next, a subtractor 210 calculates the difference between the input current command and a detected input current from a current detector 204. A regulator 211 brings this current difference to zero, and the output of the regulator 211 is added to the detected input voltage in an adder 212 in order to calculate a rectifier voltage command λREC.
Meanwhile, a PLL circuit 214 synchronizes the detected input voltage with the internal phase reference of the controller, and the output of the PLL circuit 214 is input to a carrier calculating unit 215. The carrier calculating unit 215 calculates, according to the output from the PLL circuit 214, a carrier having a frequency that changes in synchronization with the detected input voltage. This carrier is compared to the voltage command λREC in a comparator 213 in order to obtain a logical pulse PLSR. Furthermore, a dead time generator 216 adds a dead time for protecting against arm short-circuits to the logical pulse PLSR and generates a pulse PLSREC, and this pulse PLSREC is output as a signal for switching the semiconductor switching element of the rectifier converter 104 ON and OFF.
FIG. 7 is a block diagram illustrating a configuration of the carrier calculating unit 215.
In the carrier calculating unit 215, an oscillator 10 outputs a fixed-frequency pulse, which is then input to an up/down counter 20. Moreover, the output of the PLL circuit 214 illustrated in FIG. 6 is set as the upper limit for the carrier frequency, and a sign inverter 30 inverts the upper limit and sets the resulting value as the lower limit for the carrier frequency, which is also input to the up/down counter 20. As illustrated in FIG. 7, the up/down counter 20 counts the number of output pulses from the oscillator 10 between the upper limit and the lower limit in order to calculate a carrier with a prescribed frequency.
Next, the configuration and operation of the controller for the inverter converter 106 illustrated in FIG. 6 will be described.
A subtractor 217 calculates the difference between a target output voltage VA* calculated by the PLL circuit 214 and a detected output voltage VA from a voltage detector 203, and this difference is input to a regulator (an output voltage regulator) 218. The regulator 218 brings this voltage difference to zero, and the output of the regulator 218 is input to an adder 219 along with the target output voltage VA*.
Moreover, an adder 220 adds a detected output current IA of the local device (the uninterruptible power supply 100A illustrated in FIG. 5) as detected by a current detector 205 to a detected output current IB of the other device connected in parallel (the uninterruptible power supply 100B illustrated in FIG. 5) in order to calculate a load current. This load current is input to a current command calculating unit 222, which converts the load current to output current commands for each device. A subtractor 223 calculates the difference between the detected output current of the local device and the respective output current command, and this difference is input to a regulator (a load-balancing regulator) 224.
The regulator 224 brings this current difference to zero, and the output of the regulator 224 is sent to the adder 219.
The adder 219 adds together the target output voltage VA* and the outputs from the regulators 218 and 224 in order to calculate an inverter voltage command λINV. This voltage command λINV is compared to the carrier in a comparator 225 in order to obtain a logical pulse PLSI. Furthermore, a dead time generator 226 adds a dead time to the logical pulse PLSI and generates a pulse PLSINV, and this pulse PLSINV is output as a signal for switching the semiconductor switching element of the inverter converter 106 ON and OFF.
FIG. 8 illustrates the carrier, the voltage command, the logical pulse, and the output pulses that include dead time on the inverter converter 106 side. The relationships between these signals are the same on the rectifier converter 104 side.
Patent Document 1, for example, discloses a power converter that operates using a fixed-frequency carrier as described above. In Patent Document 1, the carrier frequency of a variable operating frequency voltage-type PWM inverter that drives an induction motor for a compressor is fixed to a frequency greater than or equal to 10 kHz.
However, in power converters that use a fixed-frequency carrier, components of the carrier frequency (the switching frequency) are superimposed on the voltage, and therefore as illustrated in FIG. 9, for example, currents that include harmonics flow through the reactors for each phase on the output side (here, the rectifier converter 104 and the inverter converter 106 are both three-phase circuits). FIG. 10 is a graph showing the frequency spectrum of the reactor currents as analyzed using a fast Fourier transform (FFT).
As shown in FIG. 10, the reactor current spectrum exhibits peaks near integer multiples of the carrier frequency (indicated by the dashed vertical lines in FIG. 10), and therefore mid-capacity to high-capacity power converters that utilize a carrier frequency of less than or equal to 10 kHz such as 5 kHz, for example, will generate an audible and unpleasant magnetostrictive noise due to the peaks p′ shown in FIG. 10.
Patent Document 2, for example, discloses a technology for randomly changing the carrier frequency in order to reduce such magnetostrictive noise.
FIG. 11 conceptually illustrates the frequency spectrum when the carrier frequency is changed (modulated) at random. This random modulation makes it possible to reduce the magnitude of the peaks in the spectrum.